The invention relates to microelectronic processing, and in particular to fabrication of large CCD arrays or MOS/LSI circuits in which variations in the absolute value of the MOS threshold voltage could exceed acceptable limits.
Various methods for controlling threshold voltage variation through processing techniques are known in the prior art. The threshold voltage is a function of several parameters, including the gate oxide thickness, the doping of the substrate, and the gate to silicon work function .PHI..sub.GS. The threshold voltage can therefore be controlled by precisely controlling each of these variables. In practice, however, there are always non-uniformities in all of the variables.
One prior art technique adjusts for non-uniformities in certain ones of the parameters is varying the gate oxide thickness. This technique is frequently used in the prior art but does not result in the ultimate possible reduction in the threshold voltage variation in large wafers, since the range of t.sub.ox (the gate oxide thickness) is limited by device performance considerations and the physical limits on its dielectric integrity.
Another prior art technique is to use lightly doped initial substrate material and then ion implant the channel regions so as to create a more uniform doping at the surface. Yet another prior art technique is to use polysilicon gates with as low sheet resistivity as possible. The latter technique permits the .PHI..sub.GS term, the work function between the gate and the silicon substrate, to be more uniform.
All of these techniques used together limit the threshold voltage variation to reasonable levels for most applications. However, for demanding applications using large substrate areas such as large CCD arrays or MOS/LSI circuits with a large die area such techniques still do not permit the threshold voltage variation to be within acceptable limits. One of the side effects of the fabrication process which is not affected by such prior art techniques is the problem of autodoping of gate regions adjacent to degenerate diffusions, during gate oxide growth. Such autodoping results in appreciable local and wafer scale variations in the threshold voltage which are unacceptable for certain applications and which cannot be minimized using the prior art techniques.